R&D Engineer, Sr 1 (Circuit Design Engineer)

Job Description and Requirements:-


Qualification:


Experience Required: 6+ yearsEducation: Btech/Mtech/Phd. Electronics/Electrical engineering


Skills/Experience:


- Recent experience delivering DDR I/O designs for low power wireless devices.- Solid understanding of related CMOS process technology issues in 28nm and smaller.- I/O design methodology & flow, Calibration, JTAG design requirements, understanding of analog circuitry, familiarity with basic ESD concepts.- Familiarity with ASIC flow: Synopsys libraries, LEF generation, Place & Route & understanding of top level verification flow.- DDR2/DDR3 design experience including LPDDR/LPDDR2.- General Understanding of the DDR Timing, ODT and SDRAM functionality.- Familiarity with: JEDEC requirements for DDR interfaces & standards; Power & Signal Integrity.- Additional preferred experience in design and development of GPIO's, Special high speed IO's such as LVDS, USB, MIPI, DigRf, PLL's, ADC, etc- Ability to foster accountability and ownership through hands-on technical leadership.- Excellent written and verbal communication skills in interactions with customers, and internal development teams.- 5+ year's CMOS IO circuit development expertise


Responsibilities:


- DDR/DDR2/DDR3/LPDDR/LPDDR2 I/O Circuit and layout design including GPIO and Special IO’s.- Provide subject matter expertise and technical leadership in design of high speed I/Os such as DDR.- Work with DDR PHY team, package engineers and system engineers to meet design specifications.


Interested candidates can forward their resumes to vishalka@synopsys.com