Intern (Technical)

1. Job Description: The focus of work would be in one of the following areas:USB2/USB3/Ethernet

The nature of work would be on the following lines:
Architecture exploration of the sub-blocks within one of these IPs to optimize for area, speed and power
VLSI Design & verification of these sub-blocks/exploration of latest features and standards

Requirements:

HDL Languages coding experience preferably in Verilog/Vera/System Verilog is preferable.
The candidate must have completed Bachelors degree in electronics/ Electrical engg. Partial completion of MS/MTech preferable

2. Job Description:- This Engineer will work with the Design Compiler R&D team to implement synthesis product capabilities including but not limited to Synthesis for Multi-Voltage design, usability and infrastructure enhancements. The engineer will also have to support existing functionality and strive to improve the quality  and maintainability of the software. Development will be in C. The engineer will require to perform first level debugging on any issues hit during development, using standard tools available in-house. As part of the job, the engineer will also design and develop testcases in VHDL/Verilog to test the features/bugs fixed by the individual. The engineer will also be responsible to validate the code changes across the existing Regression testing system and QoR suite. The engineer will have to adhere by the standard practices followed such as code review, testing the code through purify, testing across multiple platforms etc.

Requirements:

Graduate/Post graduate student in CS/EC with excellent C programming skills, thorough in Data Structures and Algorithms and good Digitial Design knowledge.

Knowledge of PERL, Tcl and Shell scripting; debugger(gdb); HDLs like VHDL/Verilog are an added advantage.

Should be a self learner, committed, good team player with good written/oral communication skills.

We are looking for Interns with Good Academic background. Please email me your resume at vishalka@synopsys.com