Job description:
The ideal candidate will have good background in RTL Design and directed verification. Design expertise includes evolving architectures from specifications, micro-architecting modules, design for low area/power and understanding and following good coding guidelines. Verification expertise includes concepts, definition of verilog testbench, test case development and verifying the design under test. Also the candidate should be able to define/analyze the coverage metrics.
Job responsibilities include understanding connectivity protocols like Ethernet, USB, SDMMC, AMBA, HDMI and working on the design/verification of designs in such protocols.
Be able to implement test benches and test cases in HDL like Verilog is needed. The candidate will work in a project and team oriented environment with teams spread across multiple sites worldwide
Must have BS in EE with 12+ years of relevant experience or MS with 10+ years of relevant experience in one or more of the following areas:
*Prior ASIC/IP verification skills with essential knowledge of Verilog.
*Hands on with Verilog/HVL and Simulation tools
*Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background
*Knowledge of in one or more of Ethernet/USB/SDMMC/AMBA protocol
•C/C++/system Verilog are an added advantage.
•Experience with Perforce for revision control along with Perl/Shell scripts is a plus.
Thanks for your consideration.
Interested candidates may kindly respond with the resumes at vishalka@synopsys.com
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