R&D Engineer, Sr I & Sr II (C/C++, DSP, Data Structure, Algorithm, Unix)

R&D Engineer, Sr II

Description:

This position is for the High Level Synthesis team in the Synopsys Solutions Group in Bangalore to help develop and support the Synphony Model Compiler product. Synphony Model Compiler is a library of high level DSP building blocks delivered through the Mathworks Simulink environment. Designs created with the library can be synthesized into hardware using the Synphony Model Compiler high level synthesis engine.
The candidate will be responsible for specification, design, implementation, and support of DSP library blocks. The DSP library blocks are written in C and support fixed point data types. The library blocks should be optimized for computational efficiency and runtime.
Requirements:

• Strong C/C++ programming skills
• Understanding of basic data structures
• Good problem solving skills
• Understanding of fixed-point representation and arithmetic
• Exposure to DSP designs
• Exposure to matlab/simulink environment will be a plus

R&D Engineer, Sr I

Description:

This position is for the High Level Synthesis team in the Synopsys Solutions Group in Bangalore to help develop and support the Synphony Model Compiler product. Synphony Model Compiler is a library of high level DSP building blocks delivered through the Mathworks Simulink environment. Designs created with the library can be synthesized into hardware using the Synphony Model Compiler high level synthesis engine.

We are looking for a senior engineer to design and develop innovative HLS algorithms for Model Compiler. In this role you will work on complex problems such as scheduling, binding, resource sharing, and retiming. You will design and implement sophisticated algorithms to solve such problems, and will help us deliver best –in-class quality of results (QoR). You will also help rearchitect the core software architecture used by the optimization algorithms.


Requirements:

• Strong C/C++ programming background along with excellent problem solving skills. Algorithm and data structure design skills. Strong background in graph theory and graph algorithms. Ability to assess and redesign the software architecture for the optimization algorithms. Ability to develop robust and efficient implementations for complex problems.
• Familiar with high-level synthesis optimization algorithms such as scheduling, binding, resource sharing, and retiming. Ability to deliver excellent QoR by applying innovative strategies to solve complex optimization problems efficiently.
• Familiarity with logic synthesis optimization techniques, and with FPGA architectures as well as ASIC design flows, is a plus.
• Exposure to DSP algorithms is a significant plus.

Interested candidates may kindly respond with the resumes at vishalka@synopsys.com