R&D Engineer, Sr I:- Verification IP (Bangalore)

Must:

1) 5+ years of experience in Functional Verification

2) 3+ years of experience with System Verilog

3) 1+ years of experience with OVM/UVM/VMM 

4) Have worked once in all phases of function verifications i.e. verification planning, architecture, BFM design and implementation, sequence implementation, test case, functional coverage etc.

5) Have worked in any of high speed serial I/F and have deep understanding. i.e. MIPI, HDMI, SATA, USB, PCI Express etc.

6) Know one of the scripting language(Perl/Shell/tcl/awk etc).

Optional:

1) Good understanding of Verilog/VHDL RTL

2) Have fair understanding of system level verification and can suggest new ideas for effective verification.

Please drop me an email at vishalka@synopsys.com if interested.