Description:
Synphony Model Compiler is a library of high level DSP building blocks delivered through the Mathworks Simulink environment. Designs created with the library can be synthesized into hardware using the Synphony Model Compiler high level synthesis engine.
We are looking for a key lead engineer to help architect and drive the Synphony Model Compiler product. This is a senior individual contributor role; you will work alongside the R&D Manager for the product, and will contribute to product architecture, software architecture, design and implementation of key DSP IP, as well as design and implementation of innovative system-level optimization algorithms.
You will influence the thinking and day-to-day contributions of the other members of the R&D team, in addition to delivering key differentiated capabilities as an individual contributor. In addition to working with the R&D team in Bangalore, you will work closely with the Model Compiler team in Turkey and in USA on key projects.
Requirements:
At this level, a postgraduate degree or equivalent is expected (PhD preferred).
Significant expertise in the DSP domain, with in-depth understanding of common DSP algorithms and how they can be implemented efficiently in hardware.
Strong background in optimization algorithms and strategy. Familiar with high-level synthesis optimization algorithms such as scheduling, binding, resource sharing, and retiming. Demonstrated ability to deliver high quality of results (QoR) by applying innovative strategies to solve complex optimization problems efficiently.
Familiar with FPGA architectures a as well as ASIC design flows. Good understanding of how to optimize DSP algorithms for the target hardware architecture.
Ability to lead by influence, in addition to contributing hands-on as an individual contributor.
Interested candidates may kindly respond with the resumes at vishalka@synopsys.com
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