R&D Engineer, Sr I (Location:- Bangalore)

Description:

The candidate will be part of the DesignWare IP Verification R&D team at Synopsys. He/She will be expected to to specify, design and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. He/ She will work closely with RTL designers and be part of a global team of expert Verification Engineers. Domains will include but not be limited to USB2.0, USB3.0, OTG, AMBA.


Requirements:



- BS in EE with 5+ years of relevant experience or MS with 2+ years of relevant experience in the verification of IP cores and/or SOC RTL designs.

- Must have experience in developing Verilog based test environments, developing and implementing test plans, extracting verification metrics.

- Must have strong Verilog coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.

- Familiarity with HVLs such as SystemVerilog is highly desired.

- Experience in Usage of HVL based VIP(Verification IPs)is an added advantage

- Exposure to IP design and verification processes is an added advantage.

- Working knowledge and experience of Connectivity protocols such as USB2.0, USB3.0 and AMBA is an added advantage

- It is essential that the individual has good communication skills and is able to demonstrate good analysis, debug and problem solving skills and be self driven.

- Exposure to VMM/UVM based methodologies though not essential is a definite plus.

Interested candidates may kindly respond with the resumes at vishalka@synopsys.com