R&D Engineer, II
Description:-
Responsible for designing, developing and debugging software programs in the areas of partitioning and timing for FPGAs.
*B.Tech/B.E/ M.Tech /M.E in Computer Science/Electrical Engineering with 3-4 years of experience in development of software in the EDA domain.
*Should be proficient in C/C++ programming, data structures, algorithms and digital design.
*Knowledge about FPGAs or boards or verilog/vhdl is a big plus.
Interested candidates may kindly respond with the resumes at vishalka@synopsys.com
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